1. Field of the Invention
The present invention generally relates to a semiconductor device and to a method for forming a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2011-034896, filed Feb. 21, 2011 the content of which is incorporated herein by reference.
2. Description of the Related Art
Devices such as DRAMs (Dynamic Random Access Memory) in which high integration is required have necessitated miniaturization of pattern rules with miniaturization of transistors. The STI (Shallow Trench Isolation) structure is generally employed for electrically isolating adjacent transistors in a DRAM cell. However, the patterning process for forming the STI structure has been difficult with miniaturization of the transistors. Further, a deterioration of characteristics of the transistors due to the short channel effect and an increase of contact resistance due to a decrease of a contact hole diameter occur with miniaturization of transistors.
A buried gate transistor is proposed in order to suppress such a phenomenon and promote further miniaturization of the transistors. Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-180150 and T. Schloesser, et al., International Electron Devices Meeting, p. 809-812, 2008 disclose a buried gate transistor to be used as, for example, a cell transistor of the DRAM since the buried gate transistor is suitable for high integration.